1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device and a method for manufacturing the same which prevents a wavy noise failure in a four-mask structure.
2. Description of the Related Art
With development of information society, demands for various display devices have increased. Accordingly, many efforts have been made to research and develop various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some species of the flat display devices are already applied to displays of various equipments.
Among the various flat display devices, the liquid crystal display (LCD) device has been most widely used due to advantageous characteristics of thinness, light weight, and low power consumption, whereby the LCD device substitutes for cathode ray tube (CRT). In addition to the mobile type LCD devices, such as a display for a notebook computer, LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.
Despite various technical developments in the LCD technology with applications in different fields, research in enhancing the picture quality of the LCD device has been in some respects lacking as compared to other features and advantages of the LCD device. To use LCD devices in various fields as a general display, the key to developing LCD devices lies on whether the LCD device can implement a high quality picture, such as high resolution and high luminance with a large-sized screen while still maintaining a light weight, thinness, and a low power consumption.
The general LCD device includes an LCD panel for displaying a picture image, and a driving portion for applying a driving signal to the LCD panel. The LCD panel includes first and second glass substrates bonded to each other with a predetermined spacing, and a liquid crystal layer injected between the first and second glass substrates.
The first glass substrate (TFT array substrate) includes a plurality of gate and data lines, a plurality of pixel electrodes and a plurality of thin film transistors. Here, the plurality of gate lines are formed on the first glass substrate at fixed intervals in one direction, and the plurality of data lines are formed at fixed intervals perpendicular to the plurality of gate lines. Then, the plurality of pixel electrodes of a matrix arrangement are formed in pixel regions defined by the plurality of gate and data lines crossing each other. The plurality of thin film transistors (TFT) are switched according to signals of the gate lines for transmitting signals of the data lines to the respective pixel electrodes. Also, the second glass substrate (color filter substrate) includes a black matrix layer to block light from regions of the second glass substrate except the pixel regions, R/G/B color filter layer to display colors, and a common electrode to display a picture image. In an in-plane switching mode LCD device, the common electrode is formed on the first glass substrate.
Next, a predetermined space is maintained between the first and second glass substrates by spacers, and the first and second substrates are bonded to each other by a sealant having a liquid crystal injection inlet. At this time, the liquid crystal layer is formed according to a liquid crystal injection method, in which the liquid crystal injection inlet is dipped into a container having liquid crystal while maintaining a vacuum state in the predetermined space between the first and second glass substrates. That is, the liquid crystal is injected between the first and second substrates by an osmotic action. Then, the liquid crystal injection inlet is sealed with the sealant.
The LCD device is driven according to an optical anisotropy and a polarizability of liquid crystal. Herein, liquid crystal molecules are aligned with directional characteristics so that the liquid crystal molecules respectively have long and thin shapes. In this respect, an electric field is applied to the liquid crystal to control the alignment direction of the liquid crystal molecules. That is, if the alignment direction of the liquid crystal molecules is controlled by the electric field, the light is refracted to the alignment direction of the liquid crystal molecules according to the optical anisotropy of the liquid crystal, thereby displaying the picture image. Accordingly, research and study for the TFT selectively driving the pixel electrode has focused on decreasing of the manufacturing cost by improving yield and productivity. Thus, it is required to improve TFT structure, and amorphous or polycrystalline silicon characteristics to decrease an ohmic contact resistance and to prevent lines/circuits from being disconnected.
The TFT structure has been actively studied for obtaining the large-sized and low-price LCD device and high productivity. The TFT is classified into a top gate type TFT and a bottom gate type TFT according to a position of a gate electrode. The bottom gate type TFT is referred to as an inverted staggered structure, and the top gate type TFT is referred to as a normal staggered structure. In the bottom gate type TFT, the gate electrode is first formed on a substrate. Meanwhile, in the top gate type TFT, the gate electrode is formed on a substrate after forming source/drain electrodes.
Hereinafter, an example using four masks in a method for manufacturing the bottom gate type LCD device forming the source/drain electrodes after forming the gate electrode will be described as follows. A related art LCD device and a method for manufacturing the same will be described with reference to the accompanying drawings. FIG. 1 is an expanded plan view illustrating a unit pixel of a related art LCD device, and FIG. 2 is a cross-sectional view illustrating a related art LCD device taken along lines I–I′ and II–II′ of FIG. 1.
As shown in FIGS. 1 and 2, the related art LCD device includes a gate line 32 having a gate electrode 32a on a lower substrate 31, and a data line 36a being in perpendicular to the gate line 32 to define a pixel region. Then, a source electrode 36b protrudes from the data line 36a, and a drain electrode 36c is formed at a predetermined interval from the source electrode 36b. At this time, the source electrode 36b is protruding from the data line 36a to have a ‘C’-shaped groove, and the drain electrode 36c is formed at the predetermined interval from the source electrode 36b inside the ‘C’-shaped groove. That is, a channel region is formed in a ‘C’-shape between the source and drain electrodes 36b and 36c. 
The gate electrode 32a is extending from the gate line 32, and a gate insulating layer 33 is formed on an entire surface of the lower substrate 31 including the gate line 32. Then, an active layer 34a is formed on the gate insulating layer 33 above the gate electrode 32a. The active layer 34a is formed below the data line 36a, the source/drain electrodes 36b and 36c and the channel region to have an enough width to cover the data line 36a, the source and drain electrode 36b and 36c. Here, the active layer 34a may include an amorphous silicon layer. Also, an ohmic contact layer 34b is formed between the active layer 34a and the data line 36a/source electrode 36b/drain electrode 36c except the channel region. The ohmic contact layer is formed of n+ amorphous silicon layer. Subsequently, a passivation layer 37 is formed on the entire surface of the lower substrate 31 including the data line 36a, and a contact hole 38 is formed in the passivation layer 37 at a predetermined portion of the drain electrode 36c. A transparent pixel electrode 39 is formed in the pixel region in contact with the drain electrode 36c through the contact hole 38.
To manufacture the LCD device having the aforementioned structure, four masks are required in the process steps. Hereinafter, the related art method for manufacturing the LCD device with the four masks will be described as follows. FIG. 3A to FIG. 3H are cross-sectional views illustrating manufacturing process steps of a related art LCD device taken along lines I–I′ and II–II′ of FIG. 1.
As shown in FIG. 3A, a gate metal layer is deposited on the lower substrate 31 by sputtering, and a first photoresist P/R1 is deposited on the gate metal layer. Then, an exposure and developing process is performed thereon by using a first mask, thereby forming a first photoresist P/R1 pattern for forming the gate line. After that, the gate metal layer is selectively removed by using the first photoresist P/R1 pattern as a mask, whereby the gate line 32 (FIG. 1) and the gate electrode 32a extending from the gate line 32 are formed on the lower substrate 31. Subsequently, the first photoresist P/R1 pattern is removed. Herein, the gate metal layer may be formed in a single-layer structure or dual-layer structure of chrome Cr, molybdenum Mo and aluminum Al.
Referring to FIG. 3B, the gate insulating layer 33 is formed on the entire surface of the lower substrate 31 including the gate line 32 and the gate electrode 32a. After forming the gate insulating layer 33, first and second semiconductor layers 34 and 35 (amorphous silicon layer and n+ amorphous silicon layer) and a data metal layer 36 are sequentially deposited on the lower substrate 31. Then, a second photoresist P/R2 is deposited on the data metal layer 36.
Next, as shown in FIG. 3C, an exposure and developing process is performed on the data metal layer 36 by using a second mask (half-tone mask), thereby forming a second photoresist P/R2 pattern for forming the data line at a predetermined thickness. The second mask (half-tone mask) is formed to completely exclude the light from the portion corresponding to data line, and to partially transmit the light in the portion corresponding to the channel region of the thin film transistor. Accordingly, the developed second photoresist P/R2 pattern is maintained at the predetermined (deposited) thickness in the portions of the data line and the source/drain electrodes while the developed second photoresist P/R2 pattern is relatively thin in the channel region of the thin film transistor. Next, the data metal layer 36 and the first and second semiconductor layers 34 and 35 are removed in wet or dry process by using the second photoresist P/R2 pattern.
As shown in FIG. 3D, the second photoresist P/R2 corresponding to the channel region of the thin film transistor is removed by ashing the second photoresist P/R2 pattern. At this time, the second photoresist P/R2 pattern totally becomes thin and narrow. Thus, the widths of the data line and the source/drain electrodes formed in the next process steps will be changed.
Referring to FIG. 3E, after the ashing process, the data metal layer 36 and the second semiconductor layer 35 corresponding to the channel region of the thin film transistor are etched by using the second photoresist P/R2 pattern as the mask. After forming the thin film transistor having the data line 36a, the source and drain electrodes 36b and 36c, the second photoresist P/R2 pattern is removed. Accordingly, the first semiconductor layer 34 corresponding to the channel region is exposed, thereby dividing the source and drain electrodes 36b and 36c from each other. Also, the active layer 34a comprising the first semiconductor layer 34 is formed on the gate insulating layer 33, and the ohmic contact layer 35a is formed on the active layer 34a except the channel region. At this time, the gate insulating layer 33 is formed of an inorganic insulating material such as oxide silicon SiOx or nitride silicon SiNx. The data metal layer is formed of molybdenum Mo, titanium Ti, tantalum Ta or molybdenum alloy Mo ally.
As shown in FIG. 3F, the passivation layer 37 is formed on the entire surface of the lower substrate 31 including the data line 36a by a PECVD deposition method. After that, a third photoresist P/R3 is deposited on the passivation layer 37, and an exposure and developing process is performed thereon using a third mask, thereby forming a third photoresist P/R3 pattern for exposing a predetermined portion of the drain electrode 36c. Then, the passivation layer 37 is selectively etched using the third photoresist pattern as the mask, thereby forming the contact hole 38 of FIG. 1 in the drain electrode 36c. Subsequently, the third photoresist P/R3 pattern is removed. Herein, the passivation layer 37 may be formed of an inorganic insulating material same as that of the gate insulating layer 33, or an organic insulating material such as an acrylic organic compound having a low dielectric constant, BCB and PFCB.
As shown in FIG. 3G, a transparent electrode material is deposited on the entire surface of the lower substrate 31 for being in contact with the drain electrode 36c through the contact hole 38. Then, a fourth photoresist P/R4 is deposited on the transparent electrode material, and then a fourth photoresist P/R4 pattern is formed when patterning the pixel electrode by an exposure and developing process using a fourth mask.
By selectively removing the transparent electrode material with the fourth photoresist P/R pattern as the mask, as shown in FIG. 3H, the pixel electrode 39 is formed in the pixel region. Then, the fourth photoresist P/R4 pattern is removed. The pixel electrode 39 is electrically connected to the drain electrode 36c through the contact hole 38 of FIG. 1. At this time, the active layer 34a is wider than the data line 36a. 
In the related art LCD device manufactured in the aforementioned process steps, the active layer 34a is wider than the data line 36a or the source/drain electrode 36b and 36c. After manufacturing the lower substrate (TFT array substrate) according to the aforementioned process steps, an alignment process for aligning liquid crystal molecules, a sealing and spacing process, a bonding process for bonding the first and second substrates to each other, and a scribe/brake process for dividing the lower substrate into unit cells are sequentially performed. As a result, an LCD panel of the LCD device is completed.
The LCD device displays the picture image by controlling light transmittance of ambient light. That is, the LCD device requires an additional light source such as a backlight for emitting the light to the LCD panel. However, when LCD panel receives light from the backlight, conductivity of the active layer varies because the active layer comprises the amorphous silicon layer (i.e., conductivity of the semiconductor layer varies according to light and heat). Accordingly, when the backlight is turned off, the active layer remains as the amorphous silicon layer. Meanwhile, when the backlight is turned on, the amorphous silicon layer is metallized by the light of the backlight. If the backlight is driven, the amorphous silicon layer is metallized so that it affects the data line 36a because the data line 36a is positioned above the amorphous silicon layer.
Also, the data line 36a and the pixel electrode 39 are adjoining to each other, and a capacitance is generated between the data line 36a and the pixel electrode 39, whereby a capacitance value between the pixel electrode 39 and the data line 36a is changed by turning on/off of the backlight according to turning on/off of inverter since the amorphous silicon layer is metallized. That is, when the backlight is turned on, a capacitance value between the data line 36a and the pixel electrode 39 is different than when the backlight is turned off so that a charge of the pixel electrode 39 varies. Also, the backlight may be driven according to a signal from the inverter circuit. At this time, the amorphous silicon layer may be metallized by turning on/off the backlight according to the turning on/off of the inverter. As a result, the capacitance value between the data line and the pixel electrode may be varied according as the backlight is turned on/off, thereby changing the charge of the pixel electrode.
In the related art LCD device manufactured using the four masks, an electric potential of the pixel electrode 39 may be varied according as the backlight is turned on/off so that luminance may be changed. Thus, a wavy noise phenomenon may be generated such that wave lines are continuously generated from the bottom to the top of an LCD panel.